Most semiconductor devices are built up using a number of material layers. Each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete integrated circuit. The patterning process, known as photolithography, defines the dimensions of the circuit features.
Modern semiconductor devices have a great many layers formed using very complex sequences of process steps. Process problems in the formation of any one layer can render an entire device defective. Defective devices are therefore tested to physically locate defects, in part to identify the defective layer. Identifying defective layers helps to troubleshoot device processes in an effort to increase device yield and prevent repeat failures.
One class of semiconductor devices, collectively known as programmable logic devices (PLDs), includes complex devices with extensive routing resources. The routing resources are typically collections of parallel metal lines formed using overlapping and isolated metal layers. The metal lines in a given layer are minimally spaced to reduce their impact on device area, and are consequently susceptible to so-called “bridge” defects that join adjacent wire conductors. These conductors are also exceptionally small in cross section, and are consequently susceptible to opens, points along a given connector that are undesirably electrically disconnected.
Opens, bridging defects, and other defects result from process problems associated with the metal layer in which the defective resource is formed. It is therefore important, in troubleshooting processes that lead to defective devices, to isolate a given defect to the layer in which that defect was formed. Unfortunately, the process of locating a defect from among the myriad resources on a modern integrated circuit is complex and difficult, and typically includes stripping a device, layer-by-layer, in an attempt to visually locate a defect identified using some conventional test pattern. There is therefore a need for improved methods of identifying defective device layers and localizing defects.